The adoption of an SOI (Silicon On Insulator) substrate has been examined for achieving the improvement in performances of LSI such as the reduction of power consumption and the speed-up.
For example, in the process disclosed in Japanese Patent Application Laid-Open Publication No. 2007-103492 (Patent Document 1), when forming a LOCOS layer (15) on an SOI substrate (10) and then forming an n type SOI transistor (100) in an element region surrounded by the LOCOS layer (15), boron (B) for preventing a parasitic channel is introduced into an end part (30) of a channel region. Also, fluorine (F) or carbon (C) is introduced as a diffusion suppressing atom for suppressing the diffusion of B into the end part (30) of the channel region (see FIG. 2 and paragraphs [0029] to [0033]). By introducing the diffusion suppressing atom in this manner, the diffusion of B in the end part (30) of the channel region is suppressed, and the reduction in the concentration of B in the end part (30) of the channel region can be suppressed. By this means, since the formation of the parasitic channel which is easily inverted to an n type can be suppressed, it is possible to provide a semiconductor device having such features as small leakage current, high speed operation and low power consumption.
Also, in Japanese Patent Application Laid-Open Publication No. 2011-138826 (Patent Document 2), a substrate (11) having a structurally-altered layer (12) is disclosed as a substrate for semiconductor device. As the substrate (11), a silicon substrate, a gallium-arsenic compound semiconductor substrate and others can be adopted, and the structurally-altered layer (12) is formed by implanting ions which do not form any conductivity-type region from one surface of the silicon substrate (11) in a thickness direction (see paragraphs [0034] to [0039]). Further, the Patent Document 2 discloses an SOI substrate having a crystalline insulating layer (21) formed in a region at a depth of 1 to 2 μm from an ion implantation surface of the silicon substrate (11) and the structurally-altered layer (12) formed in a region at a depth of 5 to 50 μm from the ion implantation surface of the silicon substrate (11) (see paragraphs [0068] to [0072]).
Also, Japanese Patent Application Laid-Open Publication No. 2000-31481 (Patent Document 3) indicates that the activation rate of impurities is reduced to half to one-tenth when both of boron and carbon are doped as channel impurities. For its solution, in the MOSFET disclosed in the Patent Document 3, a carbon-doped layer is provided at a position away from the surface of the silicon substrate, and thereby solving the problems of threshold variation and increase of parasitic resistance without causing the inactivation of impurities.
Also, Japanese Patent Application Laid-Open Publication No. 2008-85253 (Patent Document 4) discloses a MOSFET in which impurities are efficiently moved locally to a part of an SOI layer near an interface with a gate insulating film by excessive enhanced diffusion, and as a result, the impurity concentration on a front surface side of a channel region of a completely depleted SOI layer becomes higher than that on a buried insulating film side. Japanese Patent Application Laid-Open Publication No. 2001-110740 (Patent Document 5) discloses that an interstitial-silicon high-concentration layer with high silicon density is formed near a surface of a semiconductor substrate by the ion implantation of Si or Ge. Japanese Patent Application Laid-Open Publication No. 2001-156291 (Patent Document 6) discloses a technique in which enhanced diffusion of fluorine is effectively prevented even when fluorine is introduced in a state where channel impurities are present and Si—F bonds are efficiently formed in the channel region. More specifically, after annihilating interstitial silicon atoms generated by the ion implantation of fluorine by the first heat treatment, fluorine is moved to the channel region by the second heat treatment, and thereby forming Si—F bonds at high efficiency.
Note that numbers in parentheses in the descriptions above correspond to the reference numbers in the respective Patent Documents.